| • | 12 channel single-stop time-to-digital converter (TDC) with single-start and multi-start acquisition modes |
| • | 50 ps timing resolution |
| • | Wide range with up to 20 s between first and last events |
| • | Large internal memory buffer, with up to 512 hits per channel |
| • | Low jitter (<3 ps rms) high stability (±2 ppm) internal clock source |
| • | External 10 MHz reference input |
| • | FPGA based Data Processing Unit (DPU) |
| • | Fast readout, with DMA mode for increased data throughput |
| • | Overvoltage-protected inputs, with 50 Ω K-Lock (LEMO) connectors |
| • | Built-in self calibration |
| • | Modular, single-slot 6U PXI/CompactPCI Standard |
| • | Low power consumption (<22 W) |
